Touch display device and gate driving circuit

ABSTRACT

Embodiments of the present disclosure relate to a touch display apparatus and a gate driving circuit, and more particularly, provide a touch display apparatus including: two or more signal lines that transmit clock signals having the same frequency and different phases; and a multiplexer including input nodes through which clock signals transmitted through the two or more signal lines are input and an output node outputting any one of clock signals input to the input nodes. According to the embodiments of the present disclosure, touch sensing accuracy and display quality are possible to be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit and priority from Korean PatentApplication No. 10-2021-0129743, filed in the Republic of Korea on Sep.30, 2021, the entire contents of which are hereby incorporated byreference for all purposes as if fully set forth into the presentapplication.

BACKGROUND Technical Field

Embodiments of the present disclosure relate to a touch display device(or apparatus) and a gate driving circuit.

Description of the Related Art

As the information society develops, demands for a display device (orapparatus) for displaying an image are increasing in various forms, andin recent years, various display devices such as a liquid crystaldisplay device and an organic light emitting display device are used.

In order to provide more various functions to the user, the displaydevice may provide a function of recognizing a user's touch on thedisplay panel and performing input processing based on the recognizedtouch.

For example, a touch-recognizable display device includes multiple touchelectrodes disposed or embedded in a display panel, and may detectwhether a user touches the display panel and touch coordinates bydriving the touch electrode.

BRIEF SUMMARY

A display panel of a touch-recognizable display device may include linesfor image display and lines for touch sensing by displaying an image andproviding a touch sensing function. In some cases, lines for imagedisplay and lines for touch sensing may be disposed adjacent to eachother, and as both lines transmit signals of similar frequencies, asignal interference problem may occur between both lines. Accordingly,there are problems in that display quality is deteriorated, and touchsensing accuracy is lowered in a specific area.

One or more embodiments of the present disclosure may provide a gatedriving circuit capable of improving a screen shaking phenomenon and atouch display device with improved display quality by improving a screenshaking phenomenon.

One or more embodiments of the present disclosure may provide a gatedriving circuit capable of improving touch sensing accuracy of a touchelectrode adjacent to a non-active area and a touch display device withimproved touch sensing accuracy.

According to one embodiment of the present disclosure, there is a touchdisplay device including: two or more signal lines that transmit clocksignals having the same frequency and different phases, and amultiplexer including input nodes through which clock signalstransmitted through the two or more signal lines are input and an outputnode outputting any one of clock signals input to the input nodes.

According to another embodiment of the present disclosure, there is agate driving circuit including: a multiplexer including two or moreinput nodes and one or more output node, and a gate signal outputcircuit that receives a signal output from an output node of themultiplexer and generates a gate signal input to a sub-pixel.

According to embodiments of the present disclosure, it is possible toprovide a gate driving circuit capable of improving a screen shakingphenomenon and a touch display device with improved display quality byimproving a screen shaking phenomenon.

According to embodiments of the present disclosure, it is possible toprovide a gate driving circuit capable of improving touch sensingaccuracy of a touch electrode adjacent to a non-active area and a touchdisplay device with improved touch sensing accuracy.

The above are example technical benefits that is expected from thepresent disclosure and one or more embodiments and the combinationthereof may provide other technical benefits that are not mentionedabove. Further, the embodiments provided herein address one or moreproblems in the related art including the example technical problemidentified above.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The above and other aspects, features and advantages of the presentdisclosure will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram illustrating a touch display device according toembodiments of the present specification.

FIG. 2 is a diagram illustrating a display part in a touch displaydevice according to embodiments of the present specification.

FIG. 3 is a diagram illustrating a structure of a touch sensor in thetouch panel of the present specification.

FIG. 4 is a partial cross-sectional view of the touch panel of thepresent specification, and is a view showing an example of across-sectional structure of the portion X-X′ shown in FIG. 3 .

FIG. 5 is a block diagram illustrating a gate driving circuit accordingto embodiments of the present specification.

FIG. 6 is a diagram illustrating an example of the gate signal outputcircuit (GOC) of FIG. 5 .

FIG. 7 is a diagram for explaining why touch sensing accuracy of touchelectrodes adjacent to a non-active area is low in a touch displaydevice according to embodiments of the present specification.

FIG. 8 is a diagram illustrating a change in display quality accordingto a frequency of a gate clock signal when a frequency of a touchdriving signal is constant in a touch display device according toembodiments of the present specification.

FIG. 9 is a view for explaining a touch display device including amultiplexer.

FIG. 10 is a diagram illustrating an example of a gate signal outputcircuit to which a signal output from a multiplexer is input.

FIG. 11 is a diagram exemplarily showing a timing diagram of a gateclock signal GCLK's and a multiplexer control signal of FIG. 10 .

FIG. 12 is an example of a cross-sectional structure cut along line I-I′of FIG. 7 .

DETAILED DESCRIPTION

In the following description of examples or embodiments of the presentdisclosure, reference will be made to the accompanying drawings in whichit is shown by way of illustration specific examples or embodiments thatcan be implemented, and in which the same reference numerals and signscan be used to designate the same or like components even when they areshown in different accompanying drawings from one another. Further, inthe following description of examples or embodiments of the presentdisclosure, detailed descriptions of well-known functions and componentsincorporated herein will be omitted when it is determined that thedescription may make the subject matter in some embodiments of thepresent disclosure rather unclear. The terms such as “including,”“having,” “containing,” “constituting” “make up of,” and “formed of”used herein are generally intended to allow other components to be addedunless the terms are used with the term “only.” As used herein, singularforms are intended to include plural forms unless the context clearlyindicates otherwise.

Terms, such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be usedherein to describe elements of the present disclosure. Each of theseterms is not used to define essence, order, sequence, or number ofelements, etc., but is used merely to distinguish the correspondingelement from other elements.

When it is mentioned that a first element “is connected or coupled to,”“contacts or overlaps,” etc., a second element, it should be interpretedthat, not only can the first element “be directly connected or coupledto” or “directly contact or overlap” the second element, but a thirdelement can also be “interposed” between the first and second elements,or the first and second elements can “be connected or coupled to,”“contact or overlap,” etc., each other via a fourth element. Here, thesecond element may be included in at least one of two or more elementsthat “are connected or coupled to,” “contact or overlap,” etc., eachother.

When time relative terms, such as “after,” “subsequent to,” “next,”“before,” and the like, are used to describe processes or operations ofelements or configurations, or flows or steps in operating, processing,manufacturing methods, these terms may be used to describenon-consecutive or non-sequential processes or operations unless theterm “directly” or “immediately” is used together.

The shapes, sizes, dimensions (e.g., width, length, height, thickness,area, radius, diameter, etc.), ratios, angles, the number of elements,and the like illustrated in the accompanying drawings for describing theembodiments of the present disclosure are merely examples, and thepresent disclosure is not limited thereto.

In addition, when any dimensions, relative sizes, etc., are mentioned,it should be considered that numerical values for an elements orfeatures, or corresponding information (e.g., level, range, etc.)include a tolerance or error range that may be caused by various factors(e.g., process factors, internal or external impact, noise, etc.) evenwhen a relevant description is not specified. Further, the term “may”fully encompasses all the meanings of the term “can”.

Hereinafter, various embodiments of the present disclosure will bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a touch display device (or apparatus)100 according to embodiments of the present specification.

The touch display device 100 according to an embodiment of the presentspecification may provide a touch sensing function using a finger and/ora pen together with an image display function.

Here, the ‘pen’ may include an active pen or a passive pen. The activepen may have a signal transmission/reception function, may perform aninterlocking operation with the touch display device 100, or may haveits own power source. The passive pen may refer to a pen that does nothave a signal transmission/reception function and its own power supply.

The touch display device 100 may include an active area AA in which animage is displayed and a non-active area NA around the active area AA.

The touch display device 100 according to the embodiments of the presentspecification may be, for example, a television (TV), a monitor, or thelike, or a mobile device such as a tablet or a smart phone.

The touch display device 100 according to the embodiments of the presentspecification may include a display part configured to provide an imagedisplay function and a touch sensing part configured to provide a touchsensing function.

Hereinafter, structures of a display part and a touch sensing part ofthe touch display device 100 will be briefly described with reference toFIGS. 2 to 4 .

FIG. 2 is a diagram illustrating a display part in the touch displaydevice 100 according to embodiments of the present specification.

Referring to FIG. 2 , a display part of the touch display device 100according to embodiments of the present specification includes a displaypanel 210, a data driving circuit 220, gate driving circuits 230 a and230 b, and a display controller 240, and the like.

A plurality of data lines DL and a plurality of gate lines GL aredisposed in the active area AA of the display panel 210. A plurality ofsub-pixels SP may be disposed in a region where the plurality of datalines DL and the plurality of gate lines GL overlap.

The non-active areas LNA and RNA of the display panel 210 are areas, inwhich an input image is not displayed, and the sub-pixels SP are notdisposed, and various signal lines and a gate driving circuit 230 a and230 b may be disposed.

The data driving circuit 220 is configured to supply a data voltage tothe plurality of data lines DL to drive the plurality of data lines DL.

The gate driving circuits 230 a and 230 b are configured to drive theplurality of gate lines GL by supplying a scan signal to the pluralityof gate lines GL.

The display controller 240 supplies the data driving circuit controlsignal DCS and the gate driving circuit control signal GCS to the datadriving circuit 220 and the gate driving circuits 230 a and 230 b tocontrol the data driving circuit 220 and the gate driving circuits 230 aand 230 b.

The display controller 240 converts externally input image data to matchthe data signal format used by the data driving circuit 220 and outputsthe converted image data Data.

The display controller 240 may be a timing controller used in a typicaldisplay technology or a control device that further performs othercontrol functions including the timing controller.

The display controller 240 may be implemented as a separate componentfrom the data driving circuit 220, or may be implemented as anintegrated circuit together with the data driving circuit 220.

The data driving circuit 220 may be implemented by including at leastone source driver integrated circuit (SDIC).

Each source driver integrated circuit SDIC may include a shift register,a latch circuit, a digital-to-analog converter (DAC), an output buffer,and the like.

Each source driver integrated circuit SDIC may further include ananalog-to-digital converter (ADC) in some cases.

The gate driving circuits 230 a and 230 b may be implemented byincluding at least one gate driver integrated circuit (GDIC).

Each gate driver integrated circuit (GDIC) may include a shift register,a level shifter, and the like.

The data driving circuit 220 may be located on one side (e.g., upper orlower side) of the display panel 210, and in some cases, and may belocated on opposite sides (e.g., upper and lower sides) of the displaypanel 210 according to a driving method or a panel design.

The gate driving circuit 230 a and 230 b may be located on one side(e.g., left or right side) of the display panel 210, and may be locatedon opposite sides (e.g., left and right sides) of the display panel 210according to a driving method or a panel design.

The gate driving circuits 230 a and 230 b may be implemented in the formof a gate in panel (GIP) formed in the form of a thin film transistor onthe non-active areas LNA and RNA on the display panel 210.

The gate driving circuits 230 a and 230 b may include a scan signalgenerating circuit for outputting a scan signal used to turn on or turnoff the switching transistors included in the sub-pixels SP.

The gate driving circuits 230 a and 230 b may be arranged in a pluralityof stages (ST) in the non-active area LNA and RNA.

FIG. 3 is a diagram illustrating a structure of a touch sensor in thetouch panel of the present specification.

The touch panel 310 of the present specification may include one or moretouch electrodes for providing a touch sensing function, and at leastone touch routing line electrically connected to the touch electrodes.

The touch panel 310 may exist outside the display panel 210 of FIG. 2described above. That is, the touch panel 310 and the display panel 210may be separately manufactured and combined. Such a touch panel 310 iscalled an external type or an add-on type.

Alternatively, the touch panel 310 may be built in the display panel210. That is, when manufacturing the display panel 210, a touch sensorstructure such as a plurality of touch electrodes and a plurality oftouch routing lines constituting the touch panel 310 together withelectrodes and signal lines for driving the display may be formed. Sucha touch panel 310 is referred to as a built-in type or an in-cell type.Hereinafter, for convenience of description, the case in which the touchpanel 310 is a built-in type will be described as an example.

The touch display device 100 according to the embodiments of the presentspecification, as a capacitance-based touch sensing method, may sense atouch using a mutual capacitance method or may sense a touch using aself-capacitance method.

In the case of a touch sensing method based on a mutual capacitancemethod, a plurality of touch electrodes may be divided into a touchdriving electrode and a touch sensing electrode. A touch driving signalis applied to the touch driving electrode through a touch driving line.The touch sensing electrode is electrically connected to a touch sensingline to which a touch sensing signal is applied, and forms a capacitancewith the touch driving electrode. In this case, the touch line includingthe touch driving line and the touch sensing line may be referred to asa touch line, and the touch signal including the touch driving signaland the touch sensing signal may be referred to as a touch signal.

In the case of such a mutual capacitance-based touch sensing method, thetouch display device may detect the presence or absence of a touch andtouch coordinates, based on a change in the mutual capacitance accordingto the presence or absence of a pointer such as a finger or a pen.

In the case of a self-capacitance-based touch sensing method, each touchelectrode may perform both a role of a touch driving electrode and arole of a touch sensing electrode. That is, a touch driving signal isapplied to the touch electrode through one touch line, and a touchsensing signal transmitted from the touch electrode to which the touchdriving signal is applied is received through the same touch line.Accordingly, in the self-capacitance-based touch sensing method, thereis no distinction between the touch driving electrode and the touchsensing electrode and no distinction between the touch driving line andthe touch sensing line.

In the case of such a self-capacitance-based touch sensing method, thepresence or absence of a touch and/or touch coordinates may be detectedbased on a change in capacitance generated between a pointer such as afinger or a pen and a touch electrode.

Referring to FIG. 3 , the touch display device 100 (refer to FIG. 1 )according to embodiments of the present specification may have a touchsensing method based on mutual capacitance sensing method.

In the touch display device 100 according to the embodiments of thepresent specification, the mutual capacitance-based touch sensingstructure includes a plurality of X-touch electrode lines (X-TEL) and aplurality of Y-touch electrode lines (Y-TEL).

The plurality of X-touch electrode lines X-TEL and the plurality ofY-touch electrode lines Y-TEL may be positioned on the encapsulationunit ENCAP.

The plurality of X-touch electrode lines X-TEL may be disposed in afirst direction, and the plurality of Y-touch electrode lines Y-TEL maybe disposed in a second direction different from the first direction.

For example, the first direction may be an x-axis direction, and thesecond direction may be a y-axis direction. Conversely, the firstdirection may be a y-axis direction, and the second direction may be anx-axis direction. In addition, the first direction and the seconddirection may be orthogonal to each other, but may not be orthogonal toeach other.

The plurality of X-touch electrode lines X-TEL may include a pluralityof X-touch electrodes electrically connected to each other. Theplurality of Y-touch electrode lines Y-TEL may include a plurality ofelectrically connected Y-touch electrodes.

The plurality of X-touch electrodes and the plurality of Y-touchelectrodes may be electrodes whose functions are distinguished from eachother.

For example, the plurality of X-touch electrodes may be touch drivingelectrodes, and the plurality of Y-touch electrodes may be touch sensingelectrodes. In this case, the plurality of X-touch electrode lines X-TELcorrespond to touch driving electrode lines, and the plurality ofY-touch electrode lines Y-TEL correspond to touch sensing electrodelines.

Conversely, the plurality of X-touch electrodes may be touch sensingelectrodes, and the plurality of Y-touch electrodes may be touch drivingelectrodes. In this case, the plurality of X-touch electrode lines X-TELcorrespond to touch sensing electrode lines, and the plurality ofY-touch electrode lines Y-TEL correspond to touch driving electrodelines.

Referring to FIG. 3 , one or more touch routing lines (TL) may beincluded in the structure of the touch sensor.

The touch routing line TL may include an X-touch routing line X-TLelectrically connected to the X-touch electrode line X-TEL, and mayinclude a Y-touch routing line Y-TL electrically connected to theY-touch electrode line Y-TEL.

The X-touch electrode line X-TEL may include a plurality of X-touchelectrodes disposed in the same row (or column) and one or more X-touchelectrode connecting lines (not shown) that electrically connect them.Here, the X-touch electrode connection line electrically connecting thetwo adjacent X-touch electrodes may be a metal integrated with twoadjacent X-touch electrodes, and may be a metal to be connected to thetwo adjacent X-touch electrodes through a contact hole.

In a region where the X-touch electrode line X-TEL and the Y-touchelectrode line Y-TEL overlap, the X-touch electrode connection line andthe Y-touch electrode connection line (not shown) may cross each other.

In a region where the X-touch electrode line X-TEL and the Y-touchelectrode line Y-TEL overlap, the X-touch electrode connection line andthe Y-touch electrode connection line may cross each other. When theX-touch electrode connection line and the Y-touch electrode connectionline cross each other, the X-touch electrode connection line and theY-touch electrode connection line may be located on different layers.

To arrange the plurality of X-touch electrode lines X-TEL and theplurality of Y-touch electrode lines Y-TEL to cross each other, aplurality of X-touch electrodes, a plurality of X-touch electrodeconnection lines, a plurality of Y-touch electrodes, and a plurality ofY-touch electrode connection lines may be positioned in two or morelayers.

The plurality of X-touch electrode lines X-TEL are electricallyconnected to the corresponding X-touch pads X-TP through one or moreX-touch routing lines X-TL. That is, the outermost X-touch electrodeamong the plurality of X-touch electrodes included in one X-touchelectrode line X-TEL is electrically connected to the X-touch pad X-TPthorough the X-touch routing line X-TL.

The plurality of Y-touch electrode lines Y-TEL are electricallyconnected to the corresponding Y-touch pads Y-TP through one or moreY-touch routing lines Y-TL. That is, the outermost Y-touch electrodeamong the plurality of Y-touch electrodes included in one Y-touchelectrode line Y-TEL is electrically connected to the Y-touch pad Y-TPthorough the Y-touch routing line Y-TL.

Here, when the plurality of X-touch electrodes constituting theplurality of X-touch electrode lines X-TEL are touch driving electrodes,a plurality of touch driving signals are transmitted to the X-touchelectrode through the plurality of X-touch routing lines X-TL. Inaddition, when the plurality of Y-touch electrodes constituting theplurality of Y-touch electrode lines Y-TEL are touch sensing electrodes,the touch sensing signal generated from the plurality of Y-touchelectrodes is supplied to the touch driving circuit (not shown) throughY-touch routing line Y-TL.

At this time, the plurality of X-touch routing lines X-TL and theplurality of Y-touch routing lines Y-TL may extend along the non-activearea NA located outside the active area AA. A plurality of X-touchrouting lines X-TL and a plurality of Y-touch routing lines Y-TL maypartially overlap in the non-active area NA.

For example, when a plurality of X-touch routing lines X-TL and aplurality of Y-touch routing lines Y-TL are formed on different layersin the non-active area NA, the plurality of X-touch routing lines X-TLand the plurality of Y-touch routing lines Y-TL may overlap in somesections of the outer portion of the active area AA.

In this case, in an area adjacent to the touch pad TP, the touch routinglines X-TL and Y-TL may have a single electrode structure fortransmitting a touch signal. Alternatively, it may be formed of adouble-stacked structure connected to at least one contact hole toreduce electrical resistance to a touch signal or to prepare for adisconnection.

When the touch routing lines X-TL and Y-TL are formed in a doublestacked structure, a touch bridge line (not shown) may be positioned inthe vertical upper or vertical lower position of the touch routing linesX-TL and Y-TL, extending in the same direction as the touch routinglines X-TL and Y-TL

In the non-active area NA, one or more contact hoes electricallyconnecting the touch routing lines X-TL and Y-TL and the touch bridgeline may be formed at regular intervals.

On the other hand, when a plurality of X-touch routing lines X-TL and aplurality of Y-touch routing lines Y-TL are formed on the same layer,there may be no overlapping regions.

FIG. 4 is a partial cross-sectional view of the touch panel of thepresent specification, and is a view showing an example of across-sectional structure of the portion X-X′ shown in FIG. 3 .

In FIG. 4 , the touch electrode (e.g., the Y-touch electrode Y-TE) isillustrated in a plate shape, but this is only an example and may be ina mesh type. In addition, when the touch electrode is a mesh type, theopening of the touch electrode may be located on the light emitting areaof the sub-pixel.

A first transistor T1 that controls a current supplied to the lightemitting device ED disposed in each sub-pixel of the active region maybe disposed on the substrate SUB. The first transistor T1 may be adriving transistor configured to drive the light emitting device ED.

The first transistor T1 includes a first node electrode NE1corresponding to a gate electrode, a second node electrode NE2corresponding to any one of a source electrode or a drain electrode, athird node electrode NE3 corresponding to the other electrode of asource electrode or a drain electrode, a semiconductor layer SEMI, andthe like.

The first node electrode NE1 and the semiconductor layer SEMI mayoverlap with the gate insulating layer GI interposed therebetween. Thesecond node electrode NE2 is formed on the insulating layer INS tocontact one side of the semiconductor layer SEMI, and the third nodeelectrode NE3 is formed on the insulating layer INS to contact the otherside of the semiconductor layer SEMI.

The light emitting element ED may include a first electrode E1corresponding to an anode electrode (or a cathode electrode), a lightemitting layer EL formed on the first electrode E1, and a cathodeelectrode (or a anode electrode) formed on the light emitting layer EL,and the like.

The first electrode E1 is electrically connected to the second nodeelectrode NE2 of the first transistor T1 exposed through the pixelcontact hole penetrating the planarization layer PLN.

The light emitting layer EL is formed on the first electrode E1 of thelight emitting area provided by the bank BANK. The light-emitting layerEL is formed by stacking the hole-related layer, the light-emittinglayer, and the electron-related layer on the first electrode E1 in theorder or in the reverse order. The second electrode E2 is formed to facethe first electrode E1 with the light emitting layer EL interposedtherebetween.

The encapsulation unit ENCAP is disposed on a light emitting device EDthat is vulnerable to external moisture or oxygen, and blocks thepenetration of external moisture or oxygen.

The encapsulation unit ENCAP may be disposed as one layer, or may bedisposed as a plurality of layers PAS1, PCL, and PAS2 as shown in FIG. 4. For example, when the encapsulation unit ENCAP consists of a pluralityof layers PAS1, PCL, and PAS2, the encapsulation unit ENCAP may includeone or more inorganic encapsulation layers PAS1 and PAS2, and one ormore organic encapsulation layers PCL. As a specific example, theencapsulation unit ENCAP may be disposed in a structure in which thefirst inorganic encapsulation layer PAS1, the organic encapsulationlayer PCL, and the second inorganic encapsulation layer PAS2 aresequentially stacked.

Here, the organic encapsulation layer PCL may further include at leastone organic encapsulation layer or at least one inorganic encapsulationlayer.

The first inorganic encapsulation layer PAS1 is formed on the substrateSUB on which the second electrode E2 corresponding to the cathodeelectrode of the light emitting device ED is formed so as to be closestto the light emitting device ED. The first inorganic encapsulation layerPAS1 is formed of, for example, an inorganic insulating material capableof low-temperature deposition, such as silicon nitride (SilNx), siliconoxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al₂O₃).Since the first inorganic encapsulation layer PAS1 is deposited at a lowtemperature, the first inorganic encapsulation layer PAS1 may preventthe light emitting layer EL including an organic material vulnerable tohigh temperature from being damaged during the deposition process.

The organic encapsulation layer PCL may have a smaller area than thefirst inorganic encapsulation layer PAS1. In this case, the organicencapsulation layer PCL may be formed to expose both ends of the firstinorganic encapsulation layer PAS1.

The organic encapsulation layer PCL may serve as a buffer for relievingstress between layers due to bending of the organic light emitting touchdisplay device, and may serve to enhance planarization performance. Theorganic encapsulation layer PCL may be formed of, for example, anorganic insulating material such as acrylic resin, epoxy resin,polyimide, polyethylene, or silicon oxycarbon (SiOC).

On the other hand, when the organic encapsulation layer PCL is formedthrough the inkjet method, in the boundary area between the non-activearea NA and the active area AA, or in a dam area corresponding to apartial area within the non-active area NA, One or two or more dams DAMmay be formed.

For example, referring to FIGS. 3 and 4 together, the dam area may belocated in the non-active area NA. The dam area may be positionedbetween the active area AA and the pad area in which the plurality ofX-touch pads X-TP and the plurality of Y-touch pads Y-TP are formed. Inthe dam area, a primary dam DAM1 adjacent to the active area AA and asecondary dam DAM2 adjacent to the pad area may exist.

The one or more dams DAM disposed in the dam area may prevent the liquidorganic encapsulation layer PCL from collapsing in the non-active areaNA and encroaching on the pad area, when the liquid organicencapsulation layer PCL is laminated on the active area AA.

This effect may be greater when the primary dam DAM1 and the secondarydam DAM2 are provided, as shown in FIGS. 3 and 4 .

The primary dam DAM1 and/or the secondary dam DAM2 may be formed in asingle-layer or multi-layer structure. For example, the primary dam DAM1and/or the secondary dam DAM2 may be simultaneously formed of the samematerial as at least one of a bank BANK and a spacer (not shown). Inthis case, the dam structure may be formed without a separate maskaddition process and cost increase.

In addition, the primary dam DAM1 and/or the secondary dam DAM2 may beformed by stacking the first inorganic encapsulation layer PAS1 or thesecond inorganic encapsulation layer PAS2 on the bank BANK, as shown inFIG. 4 .

In addition, the organic encapsulation layer PCL including an organicmaterial may be positioned only on the inner surface of the primary damDAM1 as shown in FIG. 4 . Alternatively, the organic encapsulation layerPCL including an organic material may also be positioned on at least aportion of the primary dam DAM1 and the secondary dam DAM2. For example,the organic encapsulation layer PCL may be positioned on the primary damDAM1.

The second inorganic encapsulation layer PAS2 may be formed on thesubstrate SUB on which the organic encapsulation layer PCL is formed tocover the top surface and the side surface of each of the organicencapsulation layer PCL and the first inorganic encapsulation layerPAS1. The second inorganic encapsulation layer PAS2 may minimize (orreduce) or block external moisture or oxygen from penetrating into theorganic encapsulation layer PCL and the first inorganic encapsulationlayer PAS1. The second inorganic encapsulation layer PAS2 may be formedof, for example, an inorganic insulating material such as siliconnitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), oraluminum oxide (Al₂O₃).

A touch buffer layer T-BUF may be disposed on the encapsulation unitENCAP.

The touch buffer layer T-BUF may be positioned between the touch sensormetal, including an X-touch electrode (not shown), a Y-touch electrodeY-TE, an X-touch electrode connection line X-CL, and a Y-touch electrodeconnection line Y-CL, and the second electrode E2 of the light emittingdevice ED.

The touch buffer layer T-BUF may be designed such that the separationdistance between the touch sensor metal and the second electrode E2 ofthe light emitting device ED maintains a predetermined minimumseparation distance (e.g., 1 μm). Accordingly, it is possible to reduceor prevent a parasitic capacitance formed between the touch sensor metaland the second electrode E2 of the light emitting device ED, and throughthis, it is possible to prevent a decrease in touch sensitivity due tothe parasitic capacitance.

Without such a touch buffer layer T-BUF, the X-touch electrode, theY-touch electrode Y-TE, the X-touch electrode connection line X-CL andthe Y-touch electrode connection line Y-CL may be disposed on theencapsulation unit ENCAP.

In addition, the touch buffer layer T-BUF may block a chemical(developer or etchant, etc.) used in the manufacturing process of thetouch sensor metal disposed on the touch buffer layer T-BUF or moisturefrom the outside penetrating into the light emitting layer EL.Accordingly, the touch buffer layer T-BUF may prevent the light emittinglayer EL, which is vulnerable to a chemical solution or moisture, frombeing damaged.

The touch buffer layer T-BUF may be formed at a low temperature below acertain temperature (e.g., 100 degree Celsius (° C.)) to prevent damageto the light emitting layer EL including an organic material that isvulnerable to high temperatures. The touch buffer layer T-BUF may beformed of an acryl-based, epoxy-based, or siloxan-based material. Thetouch buffer layer T-BUF, which is made of an organic insulatingmaterial, and has planarization performance, may prevent each of theencapsulation layers PAS1, PCL and PAS2 constituting the encapsulationunit ENCAP from being damaged due to the bending of the touch displaydevice. The touch buffer layer T-BUF may prevent the touch sensor metalformed on the touch buffer layer T-BUF from being broken as the touchdisplay device is bent.

In some cases, the touch buffer layer T-BUF may be omitted as it is notpositioned on the encapsulation unit ENCAP. For example, the touchsensor metal may be directly disposed on the encapsulation unit ENCAPwithout disposing the touch buffer layer T-BUF by increasing thethickness of the second inorganic encapsulation layer PAS2.

According to the mutual-capacitance-based touch sensor structure,X-touch electrode lines X-TEL (see FIG. 3 ) and Y-touch electrode linesY-TEL (see FIG. 3 ) are disposed on the touch buffer layer T-BUF, andthe X-touch electrode lines X-TEL and the Y-touch electrode lines Y-TELmay be disposed to cross each other.

The Y-touch electrode lines Y-TEL may contain a plurality of Y-touchelectrodes Y-TE and a plurality of Y-touch electrode connection linesY-CL electrically connecting the plurality of Y-touch electrodes Y-TE.

Referring to FIG. 4 , the plurality of Y-touch electrodes Y-TE and theplurality of Y-touch electrode connection lines Y-CL may be positionedon different layers with the touch insulating layer ILD interposedtherebetween. In addition, the Y-touch electrodes Y-TE disposed adjacentto each other in one direction may be electrically connected to eachother through the Y-touch electrode connection line Y-CL.

The Y-touch electrode connection line Y-CL may be disposed to overlapthe bank BANK. Accordingly, it is possible to prevent a decrease in theaperture ratio due to the Y-touch electrode connection line Y-CL.

The X-touch electrode connection line X-CL is disposed on the same planeas the X-touch electrode X-TE or may be integrally formed with twoX-touch electrodes X-TE adjacent in one direction.

The X-touch electrode connection line X-CL may be disposed to overlapthe bank BANK. Accordingly, it is possible to prevent a decrease in theaperture ratio due to the X-touch electrode connection line X-CL.

Meanwhile, the Y-touch electrode line Y-TEL may be electricallyconnected to the touch driving circuit through the Y-touch routing lineY-TL and the Y-touch pad Y-TP. Similarly, the X-touch electrode lineX-TEL may be electrically connected to the touch driving circuit throughthe X-touch routing line X-TL (see FIG. 3 ) and the X-touch pad X-TP(see FIG. 3 ).

The touch driving circuit is a circuit that supplies a touch drivingsignal to the touch panel 310 and detects a touch sensing signal fromthe touch panel 310.

The touch display device 100 according to the embodiments of the presentspecification may further include a touch controller (not shown) and thelike, which senses the user's touch presence and/or touch position inthe touch panel 310 based on a touch sensing signal detected by a touchdriving circuit.

The touch driving circuit and the touch controller may be implemented asseparate parts or, in some cases, may be integrated into one part.

The X-touch pad X-TP may be formed separately from the X-touch routingline X-TL, or may be formed by extending the X-touch routing line X-TL.The Y-touch pad Y-TP may be formed separately from the Y-touch routingline Y-TL, or may be formed by extending the Y-touch routing line Y-TL.

When the X-touch pad X-TP is formed by extending the X-touch routingline X-TL and the Y-touch pad Y-TP is formed by extending the Y-touchrouting line Y-TL, the X-touch pad X-TP, the X-touch routing line X-TL,the Y-touch pad Y-TP, and the Y-touch routing line Y-TL may be made ofthe same first conductive material. Here, the first conductive materialis formed in a single-layer or multi-layer structure using, for example,a metal having high corrosion resistance and acid resistance and goodconductivity, such as aluminum (Al), titanium (Ti), copper (Cu), andmolybdenum (Mo).

For example, X-touch pad X-TP, X-touch routing line X-TL, Y-touch padY-TP and Y-touch routing line Y-TL in a first conductive material may beformed in a three-layered structure, such as Ti/Al/Ti or Mo/Al/Mo.

Meanwhile, a pad cover electrode (not shown) capable of covering theX-touch pad X-TP and the Y-touch pad Y-TP may be further disposed.

The pad cover electrode may be made of a second conductive material.Here, the second conductive material may be formed of a transparentconductive material such as ITO or IZO with strong corrosion resistanceand acid resistance. The pad cover electrode may be bonded to the touchdriving circuit by being molded to be exposed by the touch buffer layerT-BUF, or may be bonded to the circuit film on which the touch drivingcircuit is mounted.

The Y-touch routing line Y-TL may be electrically connected to theY-touch electrode Y-TE through a touch routing line contact hole, or maybe integrated with the Y-touch electrode Y-TE.

The Y-touch routing lines Y-TL may extend to the non-active area NA andpass through the top and side surfaces of the encapsulation unit ENCAP,and the top and side surfaces of the dam DAM to the Y-touch pad Y-TP.Accordingly, the Y-touch routing lines Y-TL may be electricallyconnected to the touch driving circuit through the Y-touch pad Y-TP.

The Y-touch routing line Y-TL may transmit the touch sensing signal fromthe Y-touch electrode Y-TE to the touch driving circuit, or receive thetouch driving signal from the touch driving circuit to Y-touch electrodeY-TE.

The X-touch routing line X-TL may be electrically connected to theX-touch electrode through a touch routing line contact hole, or may beintegrated with the X-touch electrode X-TE.

The X-touch routing lines X-TL may extend to the non-active area NA andpass through the top and side surfaces of the encapsulation unit ENCAP,and the top and side surfaces of the dam DAM to the X-touch pad X-TP.Accordingly, the X-touch routing lines X-TL may be electricallyconnected to the touch driving circuit through the X-touch pad X-TP.

The X-touch routing line X-TL may receive a touch driving signal fromthe touch driving circuit and transfer a touch driving signal to theX-touch electrode X-TE. Alternatively, the X-touch routing line X-TL mayreceive a touch sensing signal from the X-touch electrode X-TE andtransfer the touch sensing signal to the touch driving circuit.

The arrangement of the X-touch routing line X-TL and the Y-touch routingline Y-TL may be variously changed according to panel design matters.

A touch protection layer PAC may be disposed on the X-touch electrodeX-TE and the Y-touch electrode Y-TE. This touch protection layer PAC maybe extended to the front or rear of the dam DAM and disposed on theX-touch routing lines X-TL and the Y-touch routing lines Y-TL.

Meanwhile, the cross-sectional view of FIG. 4 conceptually shows thestructure, and the position, thickness, or width of each pattern(various layers or various electrodes) may vary depending on the viewingdirection or position, and the connection structure of various patternsis also shown. It may be changed, and additional layers may exist inaddition to the several illustrated layers, and some of the illustratedvarious layers may be omitted or integrated. For example, the width ofthe bank BANK may be narrower than the drawing, and the height of thedam DAM may be lower or higher than the drawing.

In addition, the cross-sectional view of FIG. 4 is a view exemplarilyillustrating a structure in which a touch electrode, a touch routinglines TL, etc., are disposed entirely on a sub-pixel, when the touchrouting line TL is electrically connected to the touch pad TP along theinclined surface of the encapsulation unit ENCAP. When the touchelectrode TE or the like is of a mesh type, the opening of the touchelectrode TE may be positioned on the light emitting area of thesub-pixel. In addition, a color filter may be further disposed on theencapsulation unit ENCAP, and the color filter may be located on thetouch electrode TE or between the encapsulation unit ENCAP and the touchelectrode TE.

FIG. 5 is a block diagram illustrating a gate driving circuit accordingto embodiments of the present specification.

Referring to FIG. 5 , the gate driving circuit includes a gate signaloutput circuit (GOC).

Referring to FIG. 5 , the gate driving circuit may be disposed in agate-in-panel (GIP) manner in the non-active area NA of the displaypanel. The gate driving circuit may include a plurality of stages ST1,ST2, ST3, ST4, and the like.

The gate driving circuit operates based on the two-phase gate clocksignal GCLKs, the start signal GVST, the low potential gate voltage VGL,and the high potential gate voltage VGH to generate a gate output Vgate.The generated gate output signals (eg, Vgate1, Vgate2, Vgate3, Vgate4,etc.) are supplied to each sub-pixel (e.g., SP1, SP2, SP3, SP4, etc.).Each of the sub-pixels SP1, SP2, SP3, and SP4 may be electricallyconnected to different gate lines GL (refer to FIG. 2 ). For example,each of the sub-pixels SP1, SP2, SP3, and SP4 may be arranged indifferent rows from each other.

Meanwhile, as described above, the gate driving circuit may include ascan signal generating circuit and a light emitting signal generatingcircuit.

The gate signal Vgate may be a scan signal SCAN for controlling turn-onand turn-off of the switching transistor included in the sub-pixel SP.Alternatively, the gate signal Vgate may be an light emitting signal EMfor controlling turn-on and turn-off of the emission control transistorincluded in the sub-pixel SP.

Hereinafter, for convenience of description, the gate signal outputcircuit GOC will be described as a circuit configured to output the scansignal SCAN as an example. However, the embodiments of the presentspecification may be similarly applied to a case in which the gatesignal output circuit GOC is a circuit configured to output the lightemitting signal EM.

FIG. 6 is a diagram illustrating an example of the gate signal outputcircuit (GOC) of FIG. 5 .

Referring to FIG. 6 , the gate signal output circuit GOC according tothe embodiments of the present specification may include first toseventh transistors T1 to T7, an auxiliary transistor Tbv, a firstcapacitor CQ, and a second capacitor CQB.

The first transistor T1 is switched according to the second gate clocksignal GCLK2 to supply the start signal GVST to the Q1 node Q1. As shownin FIG. 6 , in some cases, two first transistors T1 may be connected inseries with each other. In this case, the second gate clock signal GCLK2may be input to each of the gate nodes of the two first transistors T1.

The second transistor T2 is switched according to the first gate clocksignal GCLK1 so that either the source electrode or the drain electrodeis electrically connected to the Q1 node Q1.

The third transistor T3 is switched according to the potential of the QBnode QB to supply the high potential gate voltage VGH to either thesource electrode or the drain electrode of the second transistor T2.

The fourth transistor T4 is switched according to the second gate clocksignal GCLK2 to supply the low-potential gate voltage VGL to the QB nodeQB.

The fifth transistor T5 is switched according to the potential of the Q1node Q1 to supply the second gate clock signal GCLK2 to the QB node QB.

The sixth transistor T6 is an output buffer whose operation iscontrolled according to the potential of the Q2 node Q2. When the sixthtransistor T6 is activated when the Q2 node Q2 is the low-potential gatevoltage VGL, the sixth transistor T6 outputs a scan signal of thelow-potential gate voltage VGL to the output node N.

The seventh transistor T7 is an output buffer whose operation iscontrolled according to the potential of the QB node QB. The seventhtransistor T7 outputs a scan signal of the high potential gate voltageVGH to the output node N when the QB node QB is activated with the highpotential gate voltage VGH.

The auxiliary transistor Tbv maintains a turned-on state by thelow-potential gate voltage VGL. The auxiliary transistor Tbv maintainsthe voltages of the Q1 node Q1 and the Q2 node Q2 substantially thesame.

The first capacitor CQ is connected between the Q2 node Q2 and theoutput node N, and may be configured to store the voltage of the Q2 nodeQ2.

The second capacitor CQB is connected between the QB node QB and theinput terminal of the high potential gate voltage VGH, and may beconfigured to store the voltage of the QB node QB.

FIG. 7 is a diagram for explaining why touch sensing accuracy of touchelectrodes adjacent to a non-active area is low in a touch displaydevice according to embodiments of the present specification.

Referring to FIG. 7 , in the touch display device 100 (see FIG. 1 )according to embodiments of the present specification, touch routingwires TL and signal lines SL are positioned in a non-active area (e.g.,LNA, RNA) outside the active area AA.

As described above, the touch routing lines TL are electricallyconnected to the X-touch electrode lines X-TEL and the Y-touch electrodelines Y-TEL disposed on the touch panel, and the X-touch electrode linesX-TEL and the Y-touch electrode lines Y-TEL include one or more touchelectrodes.

Meanwhile, a gate-in-panel (GIP) type gate driving circuit may bedisposed in at least one of the non-active areas LNA and RNA on bothsides of the display panel.

The gate driving circuit receives a gate clock signal (e.g., GCLK1,GCLK2, etc.; see FIG. 6 ) and outputs the gate signal to the gate lines.These gate clock signals (e.g., GCLK1, GCLK2, etc.; hereinafterabbreviated as GCLK) may be input to the gate driving circuit throughthe signal lines SL positioned in the non-active area LNA and RNA.

Both the touch routing lines TL and the signal lines SL may be disposedin the non-active area LNA and RNA. In order to prevent a problem ofmutual interference between the touch routing lines TL and the signallines SL, the touch routing lines TL and the signal lines SL may bedisposed on different layers. In addition, in order to prevent a problemthat interference occurs between the touch routing lines TL and thesignal lines SL, a shielding electrode (not shown) may be disposedbetween the touch routing lines TL and the signal lines SL.

However, in the process of forming the shielding electrode, if theshielding electrode is incompletely formed, interference may occurbetween the touch routing line TL and the signal line SL. The problem ofinterference between the touch routing line TL and the signal line SLmay be particularly large in the outermost touch routing line TLadjacent to the signal line SL transmitting the gate clock signal GCLK.

In the X-touch electrode line X-TEL and the Y-touch electrode line Y-TELthat are electrically connected to the outermost touch routing line TL,a problem of lowering touch sensing accuracy may occur. Theabove-described problem may be more problematic when the frequency ofthe gate clock signal GCLK and the frequency of the touch driving signalinput to the touch routing line TL are the same or similar.

The touch driving circuit TDC may supply a touch driving signal to thetouch panel and detect a touch sensing signal from the touch panel. Inthis process, due to the interference between the touch routing line TLand the signal line SL, a problem of lowering accuracy of touch sensingin some areas of the touch panel may occur.

FIG. 8 is a diagram illustrating a change in display quality accordingto a frequency of a gate clock signal when a frequency of a touchdriving signal is constant in a touch display device according toembodiments of the present specification.

Referring to FIG. 8 , when the frequency of the touch driving signal(hereinafter, abbreviated as TDS) is constant, it can be seen that thelevel of “screen shaking” (also called “screen flickering”) of the touchdisplay device 100 increases, in a range in which the frequency of thegate clock signal GCLK is the same as or similar to the frequency of thetouch driving signal TDS.

The screen shaking may be a phenomenon caused by interference betweenthe gate clock signal GCLK and the touch driving signal TDS. That is,when the signal line SL to which the gate clock signal GCLK is input isinterfered with by the touch driving signal TDS, screen shaking mayoccur.

The screen shaking level shown in the graph of FIG. 8 is a relativevalue. For example, when the screen shake level is 1, the screen shakelevel at a point in time when the screen shaking is visually recognizedby the display panel may be expressed as a relative value. Also, as therelative value of the screen shaking level is greater than 1, thevisually recognized screen shaking level may further increase. Also,when the relative value of the screen shaking level is close to 0, thescreen shaking phenomenon may be hardly recognized or there may be noscreen shaking phenomenon.

For example, referring to FIG. 8 , when the frequency of the touchdriving signal TDS input to the touch routing line is constant at about233 kHz, the screen shaking may be recognized in the range where thefrequency of the gate clock signal GCLK is about 230 kHz to about 260kHz.

When the frequency of the touch driving signal TDS is constant, afrequency band of the gate clock signal GCLK in which the screen shakingphenomenon is recognized may be defined as a high interference frequencyband.

The frequency band of the gate clock signal GCLK may be defined as anon-interference frequency band or a low-interference frequency band,when the frequency of the touch driving signal is constant and thescreen shaking is recognized as less than a certain level, or there isno screen shaking at all.

When the frequency of the touch driving signal TDS is about 233 kHz, aband in which the frequency of the gate clock signal GCLK is 230 kHz ormore and 260 kHz or less may be defined as a high interference frequencyband. In particular, referring to FIG. 8 , when the frequency of thegate clock signal GCLK is 255 kHz, the screen shaking phenomenon may bevisually recognized the most.

In addition, a band in which the frequency of the gate clock signal GCLKis less than 230 kHz and a band exceeding 260 kHz may be defined as anon-interference frequency band or a low-interference frequency band.

When the frequency of the gate clock signal GCLK belongs to anon-interference frequency band or a low-interference frequency band,screen shaking may not be visually recognized in the display panel.

Accordingly, in some embodiments, it is beneficial to have a method ofconverting the frequency band of the gate clock signal GCLK input to thesignal line SL from a high interference frequency band to anon-interference frequency band or a low interference frequency band.

FIG. 9 is a view for explaining a touch display device including amultiplexer.

Referring to FIG. 9 , the touch display device 100 (see FIG. 1 )according to embodiments of the present specification includes at leastone multiplexer (MUX).

The multiplexer MUX may be located inside the gate driving circuits 230a and 230 b. When the gate driving circuits 230 a and 230 b arepositioned in a gate-in-panel (GIP) manner, the multiplexer MUX may bedisposed in each stage ST1, ST2, ST3 and ST4, and the like.

Two or more gate clock signals GCLK's are input to the multiplexer MUX.The operation timing of the multiplexer MUX is controlled by amultiplexer control signal (MCS). The multiplexer control signal MCS maybe a type of the gate driving circuit control signal GCS.

The multiplexer MUX outputs at least one gate clock signal among the twoor more input gate clock signals GCLK's to the gate signal outputcircuit GOC.

The gate clock signal GCLK's and the multiplexer control signal MCS aretransmitted through the signal line SL located in the non-active areaNA, and may be entered to the multiplexer MUX of each of the stages ST1,ST2, ST3, and ST4.

FIG. 10 is a diagram illustrating an example of a gate signal outputcircuit to which a signal output from a multiplexer is input. FIG. 11 isa diagram exemplarily showing a timing diagram of a gate clock signalGCLK's and a multiplexer control signal of FIG. 10 .

Referring to FIG. 10 , the multiplexer MUX may include twosub-multiplexers SUB MUX1 and SUB MUX2.

At least two gate clock signals GCLK1-1 and GCLK1-2 are input to thefirst sub-multiplexer SUB MUX1. The 1-1 gate clock signal GCLK1-1 isinput to a first node N1 that is an input node of the firstsub-multiplexer SUB MUX1. The 1-2 gate clock signal GCLK1-2 is input tothe second node N2 that is another input node of the firstsub-multiplexer SUB MUX1.

The operation timing of the first sub multiplexer SUB MUX1 is determinedby the multiplexer control signal MCS. The first sub-multiplexer SUBMUX1 outputs either a signal input to the first node N1 or a signalinput to the second node N2 to a third node N3 serving as an outputnode. The first sub-multiplexer SUB MUX1 may include a switching elementwhose operation timing is controlled by the multiplexer control signalMCS.

A signal output from the third node N3 of the first sub-multiplexer SUBMUX1 is input to a node (that is, a gate node of the second transistorT2 and a source node or a drain node of the sixth transistor T6) towhich the first gate clock signal GCLK1 is input of the gate signaloutput circuit GOC. Hereinafter, a signal output from the firstsub-multiplexer SUB MUX1 and input to the gate node of the secondtransistor T2 is referred to as a first gate clock signal GCLK1.

Referring to FIGS. 10 and 11 , the first sub-multiplexer SUB MUX1 mayelectrically connect the first node N1 and the third node N3 when thevoltage level of the multiplexer control signal MCS is either one of ahigh level or a low level. The first sub-multiplexer SUB MUX1 mayelectrically connect the second node N2 and the third node N3 when thevoltage level of the multiplexer control signal MCS is either the otherof a high level or a low level. In some embodiments, the high voltagelevel refers to a logic high voltage level (e.g., a logical “1”) and thelow voltage level refers to a logic low voltage level (e.g., a logical“0”).

Meanwhile, at least two gate clock signals GCLK2-1 and GCLK2-2 are inputto the second sub-multiplexer SUB MUX2. The 2-1 gate clock signalGCLK2-1 is input to the first node N1 which is an input node of thesecond sub-multiplexer SUB MUX2. The 2-2 gate clock signal GCLK2-2 isinput to the second node N2, which is another input node of the secondsub multiplexer SUB MUX2. The second sub-multiplexer SUB MUX2 mayinclude a switching element whose operation timing is controlled by themultiplexer control signal MCS.

The operation timing of the second sub multiplexer SUB MUX2 isdetermined by the multiplexer control signal MCS. The secondsub-multiplexer SUB MUX2 outputs either a signal input to the first nodeN1 or a signal input to the second node N2 to a third node N3 serving asan output node. The second sub-multiplexer SUB MUX2 may include aswitching element whose operation timing is controlled by themultiplexer control signal MCS.

A signal output from the third node N3 of the second sub-multiplexer SUBMUX2 is input to a node (that is, a gate node of the first transistor T1and a gate node of the fourth transistor T4) to which the second gateclock signal GCLK2 is input of the gate signal output circuit GOC.Hereinafter, a signal output from the second sub-multiplexer SUB MUX2and input to the gate node of the first transistor T1 is referred to asa second gate clock signal GCLK2.

Referring to FIGS. 10 and 11 , the second sub-multiplexer SUB MUX2 mayelectrically connect the first node N1 and the third node N3 when thevoltage level of the multiplexer control signal MCS is either one of ahigh level or a low level. The second sub-multiplexer SUB MUX2 mayelectrically connect the second node N2 and the third node N3 when thevoltage level of the multiplexer control signal MCS is either the otherof a high level or a low level.

The multiplexer control signal MCS input to the first sub-multiplexerSUB MUX1 and the second sub-multiplexer SUB MUX2 may be the same signal.One input line configured to transmit the multiplexer control signal MCSis disposed in the non-active area NA, so that both sub-multiplexers SUBMUX1 and SUB MUX2 may be controlled.

Hereinafter, for convenience of description, it is assumed that thefirst sub-multiplexer SUB MUX1 and the second sub-multiplexer SUB MUX2,electrically connect the first node N1 and the third node N3 when thevoltage level of the multiplexer control signal MCS is at a high level,and electrically connect the second node N2 and the third node N3 whenthe voltage level of the multiplexer control signal MCS is at a lowlevel.

Referring to FIG. 11 , the frequencies of the 1-1 gate clock signalGCLK1-1 and the 1-2 gate clock signal GCLK1-2, input to the firstsub-multiplexer SUB MUX1, are ½ (half) of the frequency of the firstgate clock signal GCLK1 input to the gate signal output circuit GOC.

In addition, the frequencies of the 2-1 gate clock signal GCLK2-1 andthe 2-2 gate clock signal GCLK2-2, input to the second sub-multiplexerSUB MUX2, are ½ (half) of the frequency of the second gate clock signalGCLK2 input to the gate signal output circuit GOC.

During a period in which the voltage level of the multiplexer controlsignal MCS is at a high level, the multiplexer MUX outputs the 1-1 gateclock signal GCLK1-1 and the 2-1 gate clock signal GCLK2-1 respectivelyas a gate signal to the gate signal output circuit GOC.

During a period in which the voltage level of the multiplexer controlsignal MCS is at a low level, the multiplexer MUX may output the 1-2gate clock signal GCLK1-2 and the 2-2 gate clock signal GCLK2-2respectively to the gate signal output circuit GOC.

Each of the 1-1 gate clock signal GCLK1-1 and the 1-2 gate clock signalGCLK1-2 includes a high level voltage period of one horizontal signalperiod 1H, and a low level voltage period of three horizontal signalperiod 3H during one period. Each of the 2-1 gate clock signal GCLK2-1and the 2-2 gate clock signal GCLK2-2 includes a low level voltageperiod of one horizontal signal period 1H, and a high level voltageperiod of three horizontal signal period 3H during one period.

The phase difference between the 1-1 gate clock signal GCLK1-1 and the1-2 gate clock signal GCLK1-2 is 180 degrees (180°). The phasedifference between the 2-1 gate clock signal GCLK2-1 and the 2-2 gateclock signal GCLK2-2 is 180 degrees (180°).

In a period in which the voltage level of the 1-1 gate clock signalGCLK1-1 is at a high level, the voltage level of the 2-1 gate clocksignal GCLK2-1 is at a low level. In a period in which the voltage levelof the 1-1 gate clock signal GCLK1-1 is at a low level, the voltagelevel of the 2-1 gate clock signal GCLK2-1 is at a high level.

In a period in which the voltage level of the 1-2 gate clock signalGCLK1-2 is at a high level, the voltage level of the 2-2 gate clocksignal GCLK2-2 is at a low level. In a period in which the voltage levelof the 1-2 gate clock signal GCLK1-2 is at a low level, the voltagelevel of the 2-2 gate clock signal GCLK2-2 is at a high level.

The multiplexer control signal MCS is a signal having a high-levelvoltage period of two horizontal signal periods 2H and a low-levelvoltage period of two horizontal signal periods 2H for one period.

The length of a period of multiplexer control signal MCS may be the sameas the 1-1 gate clock signal GCLK1-1, the 1-2 gate clock signal GCLK1-2,the 2-1 gate clock signal GCLK2-1 and the 2-2 gate clock signal GCLK2-2.As an example, the period of the signals may equal to 4 horizontalperiods 4H.

The length of one horizontal period 1H may be defined as a length of aperiod in which the gate signal Vgate of the turn-on level voltage isinput to the sub-pixel SP.

Hereinafter, with reference to FIG. 11 , a 1-1 gate clock signalGCLK1-1, a gate clock signal GCLK1-2, a 2-1 gate clock signal GCLK2-1and a 2-2 gate clock signal GCLK2-2 in one period of the multiplexercontrol signal MCS, will be described.

Referring to FIG. 11 , during the first horizontal period, the voltagelevel of the multiplexer control signal MCS is at a high level, and themultiplexer MUX outputs a 1-1 gate clock signal GCLK1-1 and a 2-1 gateclock signal GCLK2-1.

Accordingly, a high level of 1-1 gate clock signal GCLK1-1 is input tothe first gate clock signal input node of the gate signal output circuitGOC, and a low level of 2-1 gate clock signal GCLK2-1 is input to thesecond gate clock signal input node of the gate signal output circuitGOC.

Referring to FIG. 11 , during the second horizontal signal period, thevoltage level of the multiplexer control signal MCS is at a low level,and the multiplexer MUX outputs the 1-2 gate clock signal GCLK1-2 andthe 2-2 gate clock signal GCLK2-2.

Accordingly, a low level of 1-2 gate clock signal GCLK1-2 is input tothe first gate clock signal input node of the gate signal output circuitGOC, and a high level of 2-2 gate clock signal GCLK2-2 is input to thesecond gate clock signal input node of the gate signal output circuitGOC.

Referring to FIG. 11 , during the third horizontal signal period, thevoltage level of the multiplexer control signal MCS is at a low level,and the multiplexer MUX outputs the 1-2 gate clock signal GCLK1-2 andthe 2-2 gate clock signal GCLK2-2.

Accordingly, a high level of 1-2 gate clock signal GCLK1-2 is input tothe first gate clock signal input node of the gate signal output circuitGOC, and a low level of 2-2 gate clock signal GCLK2-2 is input to thesecond gate clock signal input node of the gate signal output circuitGOC.

Referring to FIG. 11 , during the fourth horizontal signal period, thevoltage level of the multiplexer control signal MCS is at a high level,and the multiplexer MUX outputs the 1-1 gate clock signal GCLK1-1 andthe 2-1 gate clock signal GCLK2-1.

Accordingly, a low level of 1-1 gate clock signal GCLK1-1 is input tothe first gate clock signal input node of the gate signal output circuitGOC, and a high level of 2-1 gate clock signal GCLK2-1 is input to thesecond gate clock signal input node of the gate signal output circuitGOC.

In summary, by using four gate clock signals GCLK1-1, GCLK1-2, GCLK2-1and GCLK2-2 having a length of one period of four horizontal periods 4H,it is possible to generate two gate clock signals GCLK1 and GCLK2 havinga period of two horizontal periods 2H.

The gate signal output circuit GOC may operate as in FIG. 6 describedabove, and below, driving of the gate signal output circuit GOC will bebriefly described with reference to FIGS. 10 and 11 .

In the first horizontal period and the second horizontal period, thestart signal GVST has a high level voltage, and the gate signal outputcircuit GOC outputs the high potential gate voltage VGH from the outputnode N. A gate signal Vgate of a turn-off level voltage (e.g., a highpotential gate voltage VGH) is output to the output node N.

In the third horizontal period, the start signal GVST has a low levelvoltage, and the gate signal output circuit GOC outputs the highpotential gate voltage VGH at the output node N. At the same time, thevoltage output from the output node N may be referred to as a voltage ofa signal input to the input node of the first gate clock signal GCLK1. Agate signal of a turn-off level voltage (e.g., a high potential gatevoltage VGH) is output to the output node N.

In the fourth horizontal period, the start signal GVST has a high levelvoltage. The gate signal output circuit GOC outputs a signal input fromthe output node N to the first gate clock signal GCLK1 input node. Here,the signal output from the output node N is a gate signal of a turn-onlevel voltage (e.g., a low potential gate voltage VGL).

In the fifth and sixth horizontal periods, the start signal GVST has ahigh level voltage, and the gate signal output circuit GOC outputs thehigh potential gate voltage VGH to the output node N. A gate signalhaving a turn-off level voltage is output to the output node N.

Accordingly, the gate signal output circuit GOC may output a signal suchas a waveform output from the output node N as a gate signal. The outputgate signal may be input to the sub-pixel SP through the gate line.

Referring to FIGS. 9 to 11 , in the gate driving circuits 230 a and 230b according to the embodiments of the present specification, amultiplexer MUX may be disposed in each stage ST1, ST2, ST3, ST4, andthe like. Through the signal line SL, the 1-1 gate clock signal GCLK1-1,the 1-2 gate clock signal GCLK1-2, the 2-1 gate clock signal GCLK2-1,the 2-2 gate clock signal GCLK2-2, the start signal GVST, and themultiplexer control signal MCS are transmitted to the gate drivingcircuits 230 a and 230 b.

The frequency of the gate clock signals (e.g., GCLK1-1 to GCLK2-2)transmitted to the gate driving circuits 230 a and 230 b through thesignal line SL may be about half of the frequency of the first gateclock signal GCLK1 and the frequency of the second gate clock GCLK2.

Accordingly, in the touch display device 100 according to theembodiments of the present specification, a problem may be resolved inwhich the touch sensing accuracy of the touch electrodes adjacent to thenon-active area NA is lowered or the screen shaking of the active areaAA, even if the frequencies of the first gate clock signal GCLK1 and thesecond gate clock signal GCLK2 are included in the interferencefrequency band.

FIG. 12 is an example of a cross-sectional structure cut along line I-I′of FIG. 7 .

Referring to FIG. 12 , according to the embodiments of the presentspecification, a plurality of signal lines SL and a plurality of touchrouting lines (e.g., TL0 to TL6) may be located in the non-active areaNA of the touch display device 100.

The plurality of signal lines SL may be disposed on the substrate SUB,and a gate insulating layer GI is disposed on the plurality of signallines SL. The plurality of signal lines SL shown in FIG. 12 may beconfigured to transmit the gate clock signal GCLK's and the multiplexercontrol signal MCS to the gate driving circuits 230 a and 230 b.

For example, referring to FIG. 12 , the plurality of signal lines SL mayinclude one or more wirings that transmit a gate clock signal forgenerating the scan signal SCAN. The plurality of signal lines SL mayinclude one or more wirings that transmit a gate clock signal forgenerating the light emitting signal EM. The plurality of signal linesSL may include one or more wirings for transmitting the multiplexercontrol signal MCS for controlling the multiplexer MUX.

Although not shown, the touch display device 100 according to theembodiments of the present specification may further include a gatesignal output circuit GOC configured to generate a light emittingsignal, a plurality of lines configured to transmit four gate clocksignals GCLK's, a multiplexer MUX disposed in front edge of the gatesignal output circuit GOC, and a line configured to transmit themultiplexer control signal MCS for controlling the multiplexer MUX andthe like.

The plurality of signal lines SL may be disposed to face the first metalM1 with the gate insulating layer GI interposed therebetween.

Here, the first metal M1 may function as a shielding electrode toprevent interference between the signal line SL and the touch routingwiring TL. The first metal M1 may be in a floating state to which noconstant voltage is applied, but a constant voltage (e.g., ELVSS) may beapplied to the first metal M1.

The first metal M1 disposed in the non-active area NA may beelectrically connected to the second electrode E2 extending from theactive area AA. The second electrode E2 may be electrically connected tothe first metal M1 through a contact hole in which a portion of theplanarization layer PLN on the first metal M1 is removed.

The second electrode E2 may be an electrode configured to apply thecommon voltage ELVSS to the light emitting devices ED included in theplurality of sub-pixels SP in the active area AA.

The second electrode E2 may extend in a direction from the inner portionI of the non-active area NA to the outer portion I′. The secondelectrode E2 may function as a shielding electrode to preventinterference between the plurality of signal lines SL and the touchrouting lines TL.

An encapsulation unit ENCAP is disposed on the second electrode E2. Theencapsulation unit ENCAP may be disposed as one layer, or may bedisposed as a plurality of layers PAS1, PCL, and PAS2. For example, whenthe encapsulation unit ENCAP consists of a plurality of layers PAS1,PCL, and PAS2, the encapsulation unit ENCAP may include one or moreinorganic encapsulation layers PAS1 and PAS2 and one or more organicencapsulation layers PCL. For example, the encapsulation unit ENCAP maybe disposed in a structure in which the first inorganic encapsulationlayer PAS1, the organic encapsulation layer PCL, and the secondinorganic encapsulation layer PAS2 are sequentially stacked.

A touch buffer layer T-BUF may be disposed on the encapsulation unitENCAP.

The touch buffer layer T-BUF may be disposed between the touch routinglines (e.g., TL0 to TL6) and the second electrode E2. The touch bufferlayer T-BUF may be designed such that the separation distance betweenthe touch routing lines TL0 to TL6 and the second electrode E2 maintainsa predetermined minimum separation distance (e.g., 1 μm). Accordingly,it is possible to reduce or prevent the parasitic capacitance formedbetween the touch routing lines TL0 to TL6 and the second electrode E2,and through this, it is possible to improve touch sensing accuracy.

The touch routing lines TL0 to TL6 may be disposed on the encapsulationunit ENCAP without the touch buffer layer T-BUF in the non-active areaNA. In this case, by increasing the thickness of the second inorganicencapsulation layer PAS2, the touch routing lines TL0 to TL6 may bedisposed on the encapsulation unit ENCAP without disposing the touchbuffer layer T-BUF.

The touch routing lines TL0 to TL6 disposed in the non-active area NAare electrically connected to the touch electrode lines disposed on thetouch panel, respectively. For example, the outermost touch routing lineTL0 may be electrically connected to the touch electrode line disposedat the outermost portion of the touch panel.

Referring to FIG. 12 , a guard electrode GUARD and a ground electrodeGND may be further disposed outside of the outermost touch routing lineTL0.

A preset voltage may be applied to the guard electrode GUARD and theground electrode GND. Accordingly, by means of the guard electrode GUARDand the ground electrode GND, it is possible to reduce/minimize theinfluence of the touch routing lines TL0 to TL6 by an electromagneticwave introduced from the outside.

The guard electrode GUARD and the ground electrode GND may be disposedon the same layer as the touch routing lines TL0 to TL6. For example,the touch routing lines TL0 to TL6, the guard electrode GUARD, and theground electrode GND may be disposed on the touch buffer layer T-BUF.The guard electrode GUARD and the ground electrode GND may be formed ofthe same material as the touch routing lines TL0 to TL6.

Referring to FIG. 12 , between the touch routing lines TL0 to TL6 andthe plurality of signal lines SL, the first metal M1 and the secondelectrode E2 may be disposed as shielding electrodes. That is, the firstmetal M1 and the second electrode E2 may physically prevent occurringinterference between the plurality of touch routing lines TL0 to TL6 andthe plurality of signal lines SL.

However, due to a process error, etc., interference may occur betweenthe outermost touch routing line TL0 and a plurality of signal lines SLdespite the presence of the first metal M1 and the second electrode E2.

In particular, when the frequency of a signal transmitted to a pluralityof signal lines SL is included in a high interference frequency bandequal to or similar to the frequency of the signal transmitted to thetouch routing lines TL, touch sensing accuracy may be lowered or displayquality may be degraded.

The touch display device according to embodiments of the presentspecification may lower the frequency of a signal (e.g., a gate clocksignal) transmitted to the signal lines SL by half by providing a gatedriving circuit including a multiplexer.

Accordingly, the frequency band of the signal transmitted to the signalline SL may be different from the frequency of the touch driving signal.For example, a frequency band of a signal transmitted to the signallines SL may be included in a non-interference frequency band or a lowinterference frequency band.

At the same time, in the touch display device according to exampleconfigurations of this specification, the frequency of the gate signalVgate input to the gate line GL may be maintained the same as before.Accordingly, it is possible to drive the touch display device at ascanning rate of 120 Hz or more.

Accordingly, touch display device 100 according to exampleconfigurations of this specification has the advantage of improvingtouch sensing accuracy and display quality compared to the conventionalone, and enabling high transfer driving.

Embodiments of the present disclosure described above will be brieflydescribed below.

According to aspects of the present disclosure, there is a touch displaydevice 100 including: two or more signal lines SL that transmit clocksignals (GCLK's; e.g., GCLK1-1, GCLK1-2, GCLK2-1, GCLK2-2, etc.) havingthe same frequency and different phases, and a multiplexer MUX includinginput nodes N1 and N2 which clock signals GCLK's transmitted through thetwo or more signal lines SL are input and an output node N3 outputtingany one of clock signals GCLK's input to the input nodes N1 and N2.

The touch display device 100 may further include a gate driving circuit230 a and 230 b including the multiplexer MUX.

The multiplexer MUX may include at least one sub-multiplexer SUB MUX,wherein the two or more signal lines SL are electrically connected tothe input nodes N1 and N2.

The gate driving circuit 230 a and 230 b may further include a gatesignal output circuit GOC to which a clock signal GCLK1 and GCLK2 fromthe multiplexer MUX is input.

The touch display device 100 may further include at least at least onetouch routing line disposed in a non-active area, and at least one touchelectrode electrically connected to the at least one touch routing line.

A signal line SL to which a multiplexer control signal MCS forcontrolling an operation timing of the multiplexer MUX is input may bedisposed in the non-active area NA, wherein the touch routing line TL isdisposed at a layer different from the two or more signal lines SLtransmitting the clock signals GCLK's.

The gate driving circuit 230 a and 230 b may be disposed in agate-in-panel (GIP) manner.

The touch display device 100 may further include a display panel 210including an active area AA in which one or more sub-pixels SP aredisposed and a non-active area NA around the active area AA, wherein twoor more signal lines SL transmitting the clock signals GCLK's and asignal line SL for transmitting a multiplexer control signal MCS forcontrolling an operation timing of the multiplexer MUX are disposed inthe non-active area NA.

A frequency of the multiplexer control signal MCS may be the same as afrequency of the clock signals GCLK's.

The two or more signal lines SL transmitting the clock signals GCLK'smay be disposed in the same layer as the signal line transmitting themultiplexer control signal.

Each of the clock signals GCLK's is either a signal for which is aperiod of high-level voltage is longer than a period of low-levelvoltage in one period or a signal for which is a period of low-levelvoltage is longer than a period of high-level voltage in one period.

The multiplexer MUX may include two or more sub-multiplexers SUB MUX1and SUB MUX2, wherein the same multiplexer control signal MCS is inputto the two or more sub-multiplexers SUB MUX1 and SUB MUX2.

According to another aspects of the present disclosure, there is a gatedriving circuit 230 a and 230 b including: a multiplexer MUX includingtwo or more input nodes N1 and N2 and one or more output node N3, and agate signal output circuit GOC that receives a signal output from anoutput node N3 of the multiplexer MUX and generates a gate signal Vgateinput to a sub-pixel SP.

The frequency of a signal GCLK's input to each of the input nodes N1 andN2 of the multiplexer MUX may be half the frequency of a signal GCLK1and GCLK2 output from the output node N3 of the multiplexer MUX.

The multiplexer MUX receives signals GCLK's with different lengths ofperiods with high voltage levels and low voltage levels during oneperiod, respectively, on two or more input nodes N1 and N2.

The above description has been presented to enable any person skilled inthe art to make and use the technical idea of the present disclosure,and has been provided in the context of a particular application and itsrequirements. Various modifications, additions and substitutions to thedescribed embodiments will be readily apparent to those skilled in theart, and the general principles defined herein may be applied to otherembodiments and applications without departing from the spirit and scopeof the present disclosure. The above description and the accompanyingdrawings provide an example of the technical idea of the presentdisclosure for illustrative purposes only. That is, the disclosedembodiments are intended to illustrate the scope of the technical ideaof the present disclosure. Thus, the scope of the present disclosure isnot limited to the embodiments shown. The scope of protection of thepresent disclosure includes all technical ideas and its equivalentsdescribed within the present disclosure.

The various embodiments described above can be combined to providefurther embodiments. These and other changes can be made to theembodiments in light of the above-detailed description. In general, inthe following claims, the terms used should not be construed to limitthe claims to the specific embodiments disclosed in the specificationand the claims, but should be construed to include all possibleembodiments along with the full scope of equivalents to which suchclaims are entitled. Accordingly, the claims are not limited by thedisclosure.

The invention claimed is:
 1. A touch display apparatus including: two ormore signal lines, in operation, that transmit clock signals including asame frequency and different phases; and a gate driving circuitincluding a multiplexer, wherein the multiplexer having at least twosub-multiplexers, each sub-multiplexer including: input nodes throughwhich the clock signals transmitted through the two or more signal linesare input; an output node outputting any one of the clock signals inputto the input nodes; and a multiplexer control signal, that in operation,controls an electrical connection between the input nodes and the outputnode, wherein a frequency of the clock signal input to the input nodesof the multiplexer is half of a frequency of a clock signal input to thegate driving circuit, wherein the clock signal input to the first inputnode of the multiplexer has a high level voltage during a first periodand the clock signal input to the gate driving circuit has a high levelvoltage during a second period, and wherein durations of the firstperiod and the second period are the same.
 2. The touch displayapparatus of claim 1, wherein the two or more signal lines areelectrically connected to the input nodes.
 3. The touch displayapparatus of claim 1, the gate driving circuit further including a gatesignal output circuit, wherein the clock signal input to the gatedriving circuit is a clock signal output from the multiplexer is input.4. The touch display apparatus of claim 1, further including: at leastone touch routing line disposed in a non-active area of the touchdisplay apparatus; and at least one touch electrode electricallyconnected to the at least one touch routing line.
 5. The touch displayapparatus of claim 4, wherein a signal line to which a multiplexercontrol signal for controlling an operation timing of the multiplexer isinput is disposed in the non-active area, and wherein the touch routingline is disposed at a layer different from the two or more signal linestransmitting the clock signals.
 6. The touch display apparatus of claim1, wherein the gate driving circuit is disposed in a gate-in-panelmanner.
 7. The touch display apparatus of claim 1, further including adisplay panel including an active area in which one or more sub-pixelsare disposed and a non-active area adjacent to the active area, whereinthe two or more signal lines transmitting the clock signals and a signalline for transmitting the multiplexer control signal for controlling anoperation timing of the multiplexer are disposed in the non-active area.8. The touch display apparatus of claim 7, wherein a frequency of themultiplexer control signal is a same as the frequency of the clocksignals.
 9. The touch display apparatus of claim 7, wherein the two ormore signal lines transmitting the clock signals are disposed in a samelayer as the signal line transmitting the multiplexer control signal.10. The touch display apparatus of claim 1, wherein each of the clocksignals, either a signal which is a period of logic high-level voltageis longer than a period of logic low-level voltage in one period or asignal which is a period of logic low-level voltage is longer than aperiod of logic high-level voltage in one period.
 11. The touch displayapparatus of claim 1, further comprising: an encapsulation unit; atleast one touch routing line disposed on the encapsulation unit at anon-active area of the touch display apparatus; and at least one touchelectrode electrically connected to the at least one touch routing line,wherein the touch routing line is disposed above the encapsulation unitand the two or more signal lines transmitting the clock signals aredisposed beneath the encapsulation unit, and wherein the touch routingline and the two or more signal lines overlap each other from a planview.
 12. A gate driving circuit including: a multiplexer including: twoor more input nodes through which clock signals including a samefrequency and different phases are input; and one or more output nodes;and a gate signal output circuit, in operation, receives a signal outputfrom an output node among the one or more output nodes of themultiplexer and generates a gate signal input to a sub-pixel, whereinthe two or more input nodes include a first input node and a secondinput node, and wherein a frequency of the clock signal input to theinput nodes of the multiplexer is half of a frequency of a clock signalinput to the gate signal output circuit.
 13. The gate driving circuit ofclaim 12, wherein the clock signal output from the output node of themultiplexer is the clock signal input to the gate output circuit. 14.The gate driving circuit of claim 12, wherein the multiplexer receivessignals with different lengths of periods with logic high voltage levelsand logic low voltage levels during one period, respectively, on two ormore input nodes.
 15. A touch display apparatus including: two or moresignal lines, in operation, that transmit clock signals including a samefrequency and different phases; and a gate driving circuit including amultiplexer, wherein the multiplexer includes: input nodes through whichthe clock signals transmitted through the two or more signal lines areinput; an output node outputting any one of the clock signals input tothe input nodes; and wherein a frequency of the clock signal input tothe input nodes of the multiplexer is half of a frequency of a clocksignal input to the gate driving circuit.
 16. The touch displayapparatus of claim 15, wherein the two or more signal lines areelectrically connected to the input nodes.
 17. The touch displayapparatus of claim 16, the gate driving circuit further including a gatesignal output circuit, wherein the clock signal input to the gatedriving circuit is a clock signal output from the multiplexer.
 18. Thetouch display apparatus of claim 16, further including: at least onetouch routing line disposed in a non-active area of the touch displayapparatus; and at least one touch electrode electrically connected tothe at least one touch routing line.
 19. The touch display apparatus ofclaim 18, wherein a signal line to which a multiplexer control signalfor controlling an operation timing of the multiplexer is input isdisposed in the non-active area, and wherein the touch routing line isdisposed at a layer different from the two or more signal linestransmitting the clock signals.
 20. The touch display apparatus of claim18, wherein the two or more signal lines transmitting the clock signalsare disposed in the non-active area.